1. Field
This disclosure relates generally to data processing systems, and more specifically, to implementation of multiple error detection schemes for a cache.
2. Related Art
Caches are typically used in data processing systems to store multiple types of information, such as instruction information and data information (e.g. operand information). Error detection schemes can be used to protect information in a cache for improved reliability. Error detection code (EDC), error correction code (ECC), and parity detection schemes are commonly used to protect information providing error detection and (with some schemes such as ECC) error correction for memories. Single bit error detection schemes such as e.g. a Parity detection scheme can be used to detect one error bit in a field of information wherein multiple bit error detection schemes such as e.g. EDC and ECC detection schemes can be used to detect multiple bit errors. However EDC and ECC codes detection schemes are more complex, and in some embodiments, utilize more bits for error detection than the bits of the data unit. Accordingly, cache performance may be reduced with the use of EDC/ECC detection schemes over the use of parity schemes.
A data system may include certain types of information where a higher emphasis on error detection is desired and a decrease in performance may be acceptable. For other types of information, error detection requirements may not be as stringent and the sacrifice in performance may not be as acceptable. What is needed is an improved data processing system.